Assessment of Cognitive Communications Interest Areas for NASA Needs and Benefits

This effort provides a survey and assessment of various cognitive communications interest areas, including node-to-node link optimization, intelligent routing/networking, and learning algorithms, and is conducted primarily from the perspective of NASA space communications needs and benefits. Areas of consideration include optimization methods, learning algorithms, and candidate implementations/technologies. Assessments of current research efforts are provided with mention of areas for further investment. Other considerations, such as antenna technologies and cognitive radio platforms, are briefly provided as well

A Fast Hybrid Transform Algorithm for Beam Digitization

The process of digitization - the conversion of analog information into a discrete signal - is essential to the function of millions of devices, from cell phones to particle accelerators. This is what allows computers to understand and process the physical world. While short signals are easily processed, longer signals can require an exponentially growing amount of computational operations. For this reason, it is necessary to develop fast algorithms which can efficiently digitize large signals. Such algorithms will allow for the production of less expensive yet more powerful computer circuitry that will open up stronger channels for communication and scientific discovery. In this presentation, we will observe a hybrid of discrete transform matrices and its sparse factorization to derive a fast algorithm. Next, the language of signal flow graphs will be utilized to connect the algebraic operations associated with the proposed algorithm to realize the system as an integrated circuit. Moving forward, the proposed algorithm will be utilized to reduce the chip area and power consumption of analog to digital converter channels

A Fast Discrete Transform for Beam Digitization

Digital beamformers are popular due to the extensive usage in digital signal processing, including applications in radar, cellular networks, microwave imaging, and radio astronomy. When digital beamformers are considered, characteristics of the analog to digital converters e.g., dynamic range and instantaneous bandwidth, and the number of complex operations performed are of paramount importance in wireless communications. In here, we observe a hybrid of discrete transform matrices as the beam digitization transform matrix and present its sparse factorization. Next, the proposed factorization will be utilized to derive a fast algorithm while reducing the arithmetic complexity. Finally, the language of signal flow graphs will be utilized to connect the algebraic operations associated with the proposed algorithm to realize the system as an integrated circuit. This work is supported by the Faculty Innovative Research in Science and Technology, ERAU, Grant 13221

Digital Architectures for UWB Beamforming Using 2D IIR Spatio-Temporal Frequency-Planar Filters

A design method and an FPGA-based prototype implementation of massively parallel systolic-array VLSI architectures for 2nd-order and 3rd-order frequency-planar beam plane-wave filters are proposed. Frequency-planar beamforming enables highly-directional UWB RF beams at low computational complexity compared to digital phased-array feed techniques. The array factors of the proposed realizations are simulated and both high-directional selectivity and UWB performance are demonstrated. The proposed architectures operate using 2's complement finite precision digital arithmetic. The real-time throughput is maximized using look-ahead optimization applied locally to each processor in the proposed massively-parallel realization of the filter. From sensitivity theory, it is shown that 15 and 19-bit precision for filter coefficients results in better than 3% error for 2nd- and 3rd-order beam filters. Folding together with Ktimes multiplexing is applied to the proposed beam architectures such that throughput can be traded for K-fold lower complexity for realizing the 2-D fan filter banks. Prototype FPGA circuit implementations of these filters are proposed using a Virtex 6 xc6vsx475t-2ff1759 device. The FPGA-prototyped architectures are evaluated using area (A), critical path delay (T), and metrics AT and AT2. The L2 error energy is used as a metric for evaluating fixed-point noise levels and the accuracy of the finite precision digital arithmetic circuits

Multi-beam 4 GHz Microwave Apertures Using Current-Mode DFT Approximation on 65 nm CMOS

A current-mode CMOS design is proposed for realizing receive mode multi-beams in the analog domain using a novel DFT approximation. High-bandwidth CMOS RF transistors are employed in low-voltage current mirrors to achieve bandwidths exceeding 4 GHz with good beam fidelity. Current mirrors realize the coefficients of the considered DFT approximation, which take simple values in $\{0, \pm1, \pm2\}$ only. This allows high bandwidths realizations using simple circuitry without needing phase-shifters or delays. The proposed design is used as a method to efficiently achieve spatial discrete Fourier transform operation across a ULA to obtain multiple simultaneous RF beams. An example using 1.2 V current-mode approximate DFT on 65 nm CMOS, with BSIM4 models from the RF kit, show potential operation up to 4 GHz with eight independent aperture beams.Comment: 7 pages, 4 figures, In: IEEE International Microwave Symposium 201

A Passive STAR Microwave Circuit for 1-3 GHz Self-Interference Cancellation

Simultaneous transmit and receive (STAR) allows full-duplex operation of a radio, which leads to doubled capacity for a given bandwidth. A circulator with high-isolation between transmit and receive ports, and low-loss from the antenna to receive port is typically required for achieving STAR. Conventional circulators do not offer wideband performance. Although wideband circulators have been proposed using parametric, switched delay-line/capacitor, and N-path filter techniques using custom integrated circuits, these magnet-free devices have non-linearity, noise, aliasing, and switching noise injection issues. In this paper, a STAR front-end based on passive linear microwave circuit is proposed. Here, a dummy antenna located inside a miniature RF-silent absorption chamber allows circulator-free STAR using simple COTS components. The proposed approach is highly-linear, free from noise, does not require switching or parametric modulation circuits, and has virtually unlimited bandwidth only set by the performance of COTS passive microwave components. The trade-off is relatively large size of the miniature RF-shielded chamber, making this suitable for base-station side applications. Preliminary results show the measured performance of Tx/Rx isolation between 25-60 dB in the 1.0-3.0 GHz range, and 50-60 dB for the 2.4-2.7 GHz range.Comment: 4 figures, 4 page

Impact of bandwidth on antenna-array noise matching

This letter expands the treatments of wideband noise analysis of antenna arrays by including bandwidth effects on beam-equivalent receiver noise temperature, (Formula presented.), and the active reflection coefficient, (Formula presented.). The particular focus of the letter is on receiver noise decorrelation in wideband systems having noise bandwidth (Formula presented.) 1 Hz. The new analysis and simulations show increase in (Formula presented.) and the departure of (Formula presented.) from that obtained using contemporary analyses for (Formula presented.) 1 Hz. Although the paper also shows that for many applications over moderate bandwidths and close connection between the receiver and array the influence of (Formula presented.) on (Formula presented.) is not significant, the simulations of a 71-element array demonstrate that the noise decorrelation due to wide (Formula presented.) can result in tens of percent (as much as 45.5% in simulations described in this letter) increase in (Formula presented.) above the low-noise amplifier minimum noise temperature, which should be taken into account at the design stage of ultra-wide band systems, such as those under investigation by, for example, the Defense Advanced Research Project Agency (DARPA) in its wideband adaptive RF protection (WARP) program and ultra-sensitive active electronically scanned array (AESA) radars for tracking stealth objects

Distributed-Proof-of-Sense: Blockchain Consensus Mechanisms for Detecting Spectrum Access Violations of the Radio Spectrum

The exponential growth in connected devices with Internet-of-Things (IoT) and next-generation wireless networks requires more advanced and dynamic spectrum access mechanisms. Blockchain-based approaches to Dynamic Spectrum Access (DSA) seem efficient and robust due to their inherited characteristics such as decentralization, immutability and transparency. However, conventional consensus mechanisms used in blockchain networks are expensive to be used due to the cost, processing and energy constraints. Moreover, addressing spectrum violations (i.e., unauthorized access to the spectrum) is not well-discussed in most blockchain-based DSA systems in the literature. In this work, we propose a newly tailored energyefficient consensus mechanism called “Distributed-Proof-of-Sense (DPoS)” that is specially designed to enable DSA and detect spectrum violations. The proposed consensus algorithm motivates blockchain miners to perform spectrum sensing, which leads to the collection of a full spectrum of sensing data. An elliptic curve cryptography-based zero-knowledge proof is used as the core of the proposed mechanism. We use MATLAB simulations to analyze the performance of the consensus mechanism and implement several consensus algorithms in a microprocessor to highlight the benefits of adopting the proposed system

Hardware Accelerated Fast FDTD of Time Dependent Maxwell’s Equations on Xilinx RF SoC

Electromagnetics, which govern the fields of wireless communications, radar, and remote sensing, are fully described using four first-order PDEs known as Maxwell’s Equations. The finite-difference time-domain (FDTD) algorithm invented by Yee in 1966 operates on a discrete space-time staggered grid-pair for the electric and magnetic fields, and solutions are obtained via leapfrog update equations. The field of computational electromagnetics makes extensive use of the FDTD algorithm for modeling involving various types of antennas, microwave filters, circuits, aerospace vehicles, and wireless systems. For accurate and dispersion-less solution, the discretization of the spatial and temporal variables require a high degree of over-sampling that is much higher than what is demanded by the Nyquist Sampling Theorem, in order for the discrete domain update equations to represent the behavior of a continuous linear PDE system. The highly-oversampled nature of FDTD results in high computational complexity and therefore long execution times on high-performance computing systems. Hardware acceleration is a technique to accelerate the computation of FDTD using application-specific integrated digital processor arrays that are custom designed for implementing FDTD without using any software at all. The hard-wired parallel computation allows very good acceleration compared to state-of-art computing solutions based on high-performance compute servers, GPU realizations, and cloud computing techniques. The talk reports on a hardware accelerator that supports real-time operation on a Xilinx RF SoC device. Comparison with GPUs are provided (interim results show better than x100)